Conceptual Paper
Volume 1 Issue 3
JVR Sudhamsu Preetham, Nethra Perli*, D Chandrasekhar, Mathangi Akhila, N Arun Vignesh and Asisa Kumar Panigrahy
November 28, 2022
Abstract
We live in a technologically advanced society. The use of diverse electronic gadgets is interwoven with even the most fundamental aspects of our daily lives. They increase and smoothen the pace of our life. The multiplier component controls the speed of most electronic systems with high-speed applications that employ the IEEE 754-2008 standard for single-precision FPUs. Several existing methods have been included to enhance the multiplier's speed of operation. They have, however, not demonstrated a substantial difference in speed, raising it by a maximum of 1.182 times.
As a result, we presented "Vedic Design," a novel algorithm with a distinctive architecture. When this was simulated in Vivado, it improved the multiplier's speed by 3.4478 times, resulting in a multiplier that is nearly 3.5 times more efficient. The gadget is better equipped to function as a result of the reduced computational path latency.
Keywords: Computational Path Delay; Latency; Vedic Multiplier; Vivado; Speed